Course contents: Introduction, Segmentation, Paging, CISC & RISC processors, Addressing Modes, Instruction Sets, Memory Hierarchies: Cache and Scratch-Pad, Memory Technologies: SRAM and SDRAM, Computer IO Interface, Buses, x86 Assembly.

At the end of the course the student will be able to:

• Describe the characteristics of CISC and RISC architectures
• Describe the maing addressing modes and their classification in CISC and RISC architectures
• Describe the basic characteristics and structure of RISC and CISC instruction repertoire
• Describe the principles and the functionality of the memory hierarchy (Cache, Scratch Pad)
• Describe the different design options of the memory hierarchy
• Describe the functionality and the characteristics of static and dynamic RAMs
• Describe the design principles of Input/Output
• Descrbe the segmentation and paging techniques for memory management
• Describe the characteristics and the structure of the X86 processor family architecture
• Design, compile debug and execute applications written in the x86 assembly language

Assessment: The final grade for the course will be the average of theory and laboratory grades (50% theory + 50% laboratory). The course’s theory has 2 sections. The first concerns the assembly x86 language and the second the basic principles of computer architecture.
Laboratory performance is assessed on the basis of examinations (oral or written) during specific laboratory exercises set by the teacher. The final grade of the laboratory will be determined by the average performance in the examined laboratory exercises.
The course exams grades are considered promotable when the grade of both written theoretical sections are at least 50/100 and the average of the laboratory and theoretical exams must be at least 50/100. The grades in the laboratory or in the theory examination cannot be maintained for the following years.